On the Design of Energy-efficient Incremental Delta- Sigma ADCs
Room 2463 (Lifts 25-26), 2/F Academic Building, HKUST

Thesis Examination Committee

Prof Xiaojun ZHANG, ISOM/HKUST (Chairperson)
Prof Amine BERMAK, ECE/HKUST (Thesis Supervisor)
Prof George Jie YUAN, ECE/HKUST (Thesis Co-supervisor)
Prof Shahriar MIRABBASI, Department of Electrical and Computer Engineering, University of British Columbia (External Examiner)
Prof Howard Cam LUONG, ECE/HKUST
Prof Kevin Jing CHEN, ECE/HKUST



With the advent of ever pervasive electronics, energy consumption is becoming more and more important. Sensor systems with their readout circuits are ubiquitous in these systems. Designing low energy circuits, to enable longer battery lifetime or energy harvesting, is crucial. The design of analog-to-digital converters (ADCs) for these breed of circuits is extremely challenging, especially when high resolutions are required.

This thesis makes two main contributions. In the first part, we examine the energy-efficiency of incremental ADCs (IADCs), by developing a theoretical model based on noise considerations. Minimum bounds of power consumption and energy-efficiency are presented. A case study and design example are presented to see how well real circuits adhere to these bounds.

In the second part, we propose a capacitor scaling technique that exploits the uneven weightage of the decimation filter, to improve the energy efficiency of the overall ADC. Coupled with a novel 3-step quantization approach, the ADC is fabricated in 0.18um technology and achieves a 102.2 dB dynamic range within a 2.04 kHz bandwidth for a state-of-the-art energy efficiency.

Room 2463 (Lifts 25-26), 2/F Academic Building, HKUST
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