Reconfigurable Digital Computing-In-Memory: Innovative Architecture Paradigm for AI Chips
Artificial Intelligence (AI) techniques have achieved great success in a wide range of applications like computer vision, natural language processing, and scientific computing. Both academia and industry have developed many AI chips for efficient AI computing from edge to cloud. However, with the fast development of AI, the model size greatly increases, bringing huge demand for computing capability and memory capacity. Therefore, AI chips usually suffer from massive data movements between compute and memory. This is also called the Von Neuman bottleneck. Computing-In-Memory (CIM) eliminates the bottleneck by integrating compute into memory, which has proved to be a promising architecture for energy-efficient AI chips. However, the mainstream CIM architectures often suffer from analog non-ideal issues and fixed in-memory data path. The two inherent drawbacks limit the accuracy and flexibility of CIM-based AI chips. In this talk, Dr. Fengbin Tu will introduce an innovative architecture paradigm Reconfigurable Digital CIM that can achieve high efficiency, high accuracy, and high flexibility simultaneously. He will talk about chip development in the recent AI era, with special discussions on two reconfigurable AI chips (Thinker in JSSC’18, Evolver in JSSC’21) and two reconfigurable digital CIM AI chips (ReDCIM, TranCIM in ISSCC’22). The fusion of digital CIM and reconfigurable computing opens up a new dimension for AI chip design, offering unprecedented opportunities for future AI computing.
Fengbin Tu is currently an Adjunct Assistant Professor in the Department of Electronic and Computer Engineering at The Hong Kong University of Science and Technology. He is also a Postdoctoral Fellow at the AI Chip Center for Emerging Smart Systems (ACCESS), Hong Kong, China. He received the Ph.D. degree from the Institute of Microelectronics, Tsinghua University, Beijing, China, in 2019, and received the B.S. degree from the School of Electronic Engineering, Beijing University of Posts and Telecommunications, Beijing, China, in 2013. Dr. Tu was a Postdoctoral Scholar at the Scalable Energy-efficient Architecture Lab (SEAL), the Department of Electrical and Computer Engineering, University of California at Santa Barbara, CA, USA, from 2019 to 2022. His research interests include AI chip, computer architecture, reconfigurable computing, and computing-in-memory. He designed the AI chip Thinker and won the 2017 ISLPED Design Contest Award. His Ph.D. dissertation was recognized by the Tsinghua Excellent Dissertation Award in 2019. He has published two books, Artificial Intelligence Chip Design in 2020, and Architecture Design and Memory Optimization for Neural Network Accelerators in 2022. Dr. Tu’s research has been published at top conferences and journals on integrated circuits and computer architecture, including ISSCC, JSSC, DAC, ISCA, MICRO, and ASPLOS.