Thesis Examination Committee

Prof Jianfeng CAI, MATH/HKUST (Chairperson)

Prof Hoi Sing KWOK, ECE/HKUST (Thesis Supervisor)

Prof Man WONG, ECE/HKUST (Thesis Co-supervisor)

Prof Hideo HOSONO, Materials Research Center for Element Strategy (MCES), Tokyo Institute of Technology (External Examiner)

Prof Zhiyong FAN, ECE/HKUST

Prof Abhishek Kumar SRIVASTAVA, ECE/HKUST

Prof Iam Keong SOU, PHYS/HKUST

Abstract

Due to their process requirements similar to the making of amorphous silicon thin-film transistors (TFTs) and relatively higher field-effect mobility (μFE), metal-oxide (MO) TFTs are being deployed in the construction of flat panel displays. The Elevated-Metal MO (EMMO) TFT technology, based on the distinct effects of oxidizing thermal annealing on the properties of MO semiconducting films under covers of different gas-permeability, reveals promising prospects. This thesis was aimed to study on architecture modification and material engineering of EMMO TFTs in the application for advanced FPDs. With establishing and analyzing an electrical design model through pixel charging and delay propagating in active-matrix displays, the development of EMMO technology should focus on improvement of inner mobility, decreasing feature size and reducing parasitic capacitance for its competitiveness in advanced FPDs. 

Dependence of annealing behaviors of the resistivity of ITZO film on gas-permeability are studied. ITZO based EMMO TFTs have been realized and characterized. Good performance metrics, such as relatively high µFE of above 20 cm2/Vs, transfer characteristics free of hysteresis and a low width-normalized off-state leakage current of at most 8.1×10-19 A /µm, were obtained. 

With the more effective method of combining the fluorination and oxidation on passivizing oxygen vacancy defects, thermally oxidized fluorinated MO channel is the optimized combination to improve the transistor scalability and reliability. With controlling the “lateral” oxidation in the homojunction, sub-micron short channel EMMO TFTs have been realized and characterized.   

With the study of the dependence of the migration of an annealing-induced junction in MO, the self-aligned EMMO architecture was proposed and achieved employing back-side flood exposure step with annealing-induced junctions self-aligned to the edges of the gate electrode. While offering the same small parasitic capacitance, the self-aligned EMMO technology further allows full oxidation of the channel region – thus improving the performance and reliability of the transistor.