Planar III-V Nanostructures on (001) Silicon: Hetero-epitaxial Growth and Device Implementations
10am
Room 2408 (Lifts 17-18), 2/F Academic Building, HKUST

Thesis Examination Committee

Prof Zhi Yu YANG, PHYS/HKUST (Chairperson)
Prof Kei May LAU, ECE/HKUST (Thesis Supervisor)
Prof Hon Ki TSANG, Department of Electronic Engineering, The Chinese University of Hong Kong (External Examiner)
Prof Andrew Wing On POON, ECE/HKUST
Prof Johnny Kin On SIN, ECE/HKUST
Prof Kam Sing WONG, PHYS/HKUST
 

Abstract

The advancement of Si based optoelectronic circuits is fueled by the minimization of device dimension and optimization of device performance. As the scaling of transistors approaches atomistic and quantum mechanical limits, excessive power dissipation and severe signal delay are becoming more and more pressing issues. III-V compounds with excellent electron transport properties have been proposed as an alternate channel material and could enable further scaling of the CMOS technology. Moreover, the light emitting attribute of III-V materials could well address the inter/intra-chip communication bottleneck encountered by present Si based microprocessors. Therefore, integrating III-V alloys with the advanced Si based CMOS processing technology is of key significance.
 
This thesis is thus devoted to the growth of III-V nano-structures on CMOS standard (001) Si substrates, and to the design of novel nano-scale device structures for potential integration on Si. First, GaAs/InGaAs nano-fins were selectively grown on nano-patterned Si, and the excellent crystalline quality is highlighted through fabricating fin-array tunnel diodes with record high room temperature negative differential resistance regions. Then, with the demonstrated fin-array tunnel junctions as basic building blocks, various digital circuits including tunneling inverters, tunneling triggers and tri-state memory cells were monolithically integrated on (001) Si substrates. 
     
Secondly, InP nano-ridges were selectively grown on nano-patterned Si by developing a unique three-step growth procedure. Stacked InGaAs quantum wires with strong two dimensional quantum confinement were embedded inside InP nano-ridge by examining the self-limiting growth mode.  Using a novel “cycled growth procedure”, multi InGaAs ridge quantum wells with excellent optical property were successfully inserted inside InP nano-ridges. The potential of the InP/InGaAs nano-ridges as nano-scale light sources is evidenced by the demonstration of the first room temperature InP/InGaAs nano-lasers with adjustable emission wavelength at telecom bands.

日期
时间
10am
地点
Room 2408 (Lifts 17-18), 2/F Academic Building, HKUST
活动形式
讲者/ 表演者:
Yu HAN
语言
英文
主办单位
电子及计算器工程学系
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