Abstract
After a short introduction of integration and its guide lines, a basic (or baseline) CMOS flow is presented. Then the three major additions to the baseline, viz. stress engineering, high-K metal gate (HKMG), and FinFET, are introduced, together with their implementation methods. Dual damascene interconnect is also briefly covered. The reasoning (or driving forces) for incorporating these major changes are then discussed, with emphases on HKMG and FinFET. To continue the trend of EOT (eq. oxide thickness) scaling to below 2nm while alleviating the direct tunneling leakage of SiON-based gate dielectricis the motivation of adopting HK insulators. To avoid the poly depletion problem for such scaled device, metal gate has to be used. The tall-and-thin device structure of FinFET makes its body-to-substrate capacitance very small, which in turn improves its sub-threshold swing, a very desirable characteristics for scaled CMOS. In addition, the effective S/D junction depth for FinFET is confined to half of the fin width, which is good for controlling short channel effect and thus device scaling.
Speaker's Biography
Dr.Ih-Chin Chen(陳一浸) received his B.S. degree from National Taiwan University, and M.S. and Ph.D. degrees from UC Berkeley, all in electrical engineering.
He has over 30 years of R&D experience in CMOS device and technology development (from 0.25um to 14nm). At the beginning, he’d worked for TI in Dallas for 11 years, working on DRAM and later logic technologies. He was a department manager and elected as a TI Fellow. Later he joined several companies in Taiwan (or China), including WSMC, TSMC, SMIC (in China), and currently UMC. In the last two, he held the position as VP of technology development.
Dr. Chen authored or co-authored more than 110 papers (among them,6 were invited papers, 25 published at IEDM, and 10 at VLSI symp.), and held more than 20 US patents. He has been a Visiting Professor at the EE graduate school of National Cheng-Kung Univ. (成功大學) and National Chiao-Tung Univ. (交通大學) for the past 5 years. He is an IEEE Fellow.
