Low Noise CMOS Circuit Techniques for Biopotential Sensing
3:30pm
Room 5508 (Lifts 25-26), 5/F Academic Building, HKUST

Thesis Examination Committee

Prof Jingshen WU, MAE/HKUST (Chairperson)
Prof Wing Hung KI, ECE/HKUST (Thesis Supervisor)
Prof Pak Kwong CHAN, School of Electrical & Electronic Engineering, Nanyang Technological University (External Examiner)
Prof Chi Ying TSUI, ECE/HKUST
Prof Philip Kwok Tai MOK, ECE/HKUST
Prof Brian Kan Wing MAK, CSE/HKUST

 

Abstract

Faithful recording of the biopotential signal is the prerequisite for the diagnosis and treatment of various diseases. Typical local field potentials of bio-signals such as ECG, EEG and ERG lie between 0.5 Hz and 500 Hz with amplitudes ranging from tens of µV to several mV. To pick-up the tiny bio-signal low-noise bio-interface circuitry is needed. This thesis focuses on the analysis of noise issues and integrated circuit designs for low-frequency biomedical applications.
 
First, the circuit-level noise reduction techniques in CMOS circuitry is investigated. Chopper stabilization and auto-zeroing are two popular techniques to mitigate low-frequency noises, but they both have issues. Chopping will generate ripple caused by the amplifier’s input offset voltage and auto-zeroing will result in the aliasing of the wideband noise. We propose to use the method of harmonic transfer matrix to analyze circuitries that employ chopping and auto-zeroing. Based on the analysis results, a ripple-free chopper amplifier prototype is proposed.
 
Second, a low-noise chopper capacitively-coupled instrumentation amplifier (CCIA) for recording bio-potential is designed. It features a digital-assisted DC-electrode offset-cancellation loop. It achieves a noise spectrum of 47 nV/sqrtHz and is capable of handling ±50 mV electrode offset.
 
Third, a low-power fully-integrated analog front-end for bio-potential sensors is proposed. The signal conditioning circuitry consists of an integrating sampler and a 12-bit SAR ADC. Measurement results show that the analog front-end achieves an in-band gain of 58dB and an input-referred noise spectrum density of 46 nV/sqrtHz that consumes 9.2 µW in total. The prototype IC has been experimented with capturing ECG on human beings.
 
Fourth, a low-power lower-jitter relaxation oscillator for on-chip low-frequency clock generation is presented. A dynamic common-gate comparator is proposed to reduce the power, and it is combined with a slope boosting technique to reduce the period jitter. The oscillator achieves period jitter of 0.025% and temperature coefficient of 70 ppm/°C while consuming 1.36 µW at 364 kHz with a 1.2 V supply.

When
Time
3:30pm
Where
Room 5508 (Lifts 25-26), 5/F Academic Building, HKUST
Event Format
Speakers / Performers:
Jiawei ZHENG
Language
English
Organizer
Department of Electronic & Computer Engineering
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