Thesis Examination Committee
Prof Richard Hau Yue SO, IEDA/HKUST (Chairperson)
Prof Patrick YUE, ECE/HKUST (Thesis Supervisor)
Prof Hao YU, Electrical and Electronic Engineering, Southern University of Science and Technology (External Examiner)
Prof Ross MURCH, ECE/HKUST
Prof Andrew POON, ECE/HKUST
Prof Jinglei YANG, MAE/HKUST
Wireline communication featuring wide bandwidth and good channel isolation has been extensively employed in applications such as massive data centers, cloud computing, etc. In wireline links, I/O transceiver works at the highest data rate and determines the communication quality. Benefitting from the advancement of process technology, the highly demanded I/O bandwidth and power efficiency have been improved dramatically over the past decades, and the trend will continue to meet the future larger data traffic boom. While Moore’s Law is coming to an end, the mainstream non-return-to-zero (NRZ) transceivers meet more stringent challenges, and four-level pulse amplitude modulation (PAM4) transceivers become popular for doubled bandwidth efficiency but with new design challenges. In this thesis, three receivers working at ~25 Gb/s or 56 Gb/s are presented to address these issues.
Firstly, a 24-Gb/s PAM4 receiver is introduced. To improve the power efficiency, 1/4-rate topology is employed, and an adaptive variable-gain rectifier based PAM4-to-NRZ decoder is proposed. The receiver was fabricated in 28-nm CMOS, and a BER of 10-11 is achieved with a bit efficiency of 1.38 pJ/bit.
Secondly, a 26-Gb/s NRZ receiver is introduced. To achieve superior power efficiency, besides the 1/4-rate topology, a linear sampling phase detector with embedded data and edge equalization for clock data recovery is proposed. The receiver was fabricated in 28-nm CMOS, and error free and 0.31 pJ/bit are achieved while compensating 14-dB channel loss.
Finally, a 56-Gb/s PAM4 receiver is introduced. To improve the equalization ability, besides the equalization in work II, adaptive CTLEs are introduced. A bang-bang phase detector with transition selection is proposed. The chip was fabricated in 40-nm CMOS process, and simulation results are given so far. The achieved bit efficiency is 0.65 pJ/bit while tolerating 9.5-dB channel loss.