Development of Novel Normally-Off Al2O3/ AIN/ III-Nitride MOS-Channel-HEMTs and MIS-HEMTs
3pm
Room 3584 (Lifts 27-28), 3/F Academic Building, HKUST

Examination Committee

Prof Yijing YAN, CHEM/HKUST (Chairperson)
Prof Kevin J CHEN, ECE/HKUST (Thesis Supervisor)
Prof Jianbin XU, Department of Electronic Engineering, The Chinese University of Hong Kong (External Examiner)
Prof Johnny K O SIN, ECE/HKUST
Prof Zhiyong FAN, ECE/HKUST
Prof Lilong CAI, MAE/HKUST

 

Abstract

Wide-bandgap GaN-based heterojunction devices have been extensively explored as promising candidates for high-voltage power switching applications owing to their superior device properties, including high breakdown electric field, low on-resistance, high switching speed, and high operation temperature. Conventional GaN-based heterojunction devices are intrinsically normally-on because of the polarization-induced two-dimensional electron-gas (2DEG) at the heterostructure interface. However, in power electronics systems, normally-off GaN transistors are highly preferred for the inherent fail-safe operation and simpler gate drive circuit configurations. Gate recess technique is a widely utilized approach for fabricating normally-off GaN MOS-structure devices with partially or fully recessed gate region by dry etching process. These devices are usually confronted with challenges in poor controllability of recess depth and damages at III-Nitride surface induced by dry etching, and high-density interface/border traps at gate-dielectric/III-Nitride interface.

This thesis focuses on developing novel techniques to improve device performance in normally-off GaN MOS-channel-HEMTs and MIS-HEMTs. First, a novel Al2O3/AlN/GaN MOS-channel structure is presented, which features a fully recessed gate region by a digital etching technique and an in situ AlN interfacial layer. The MOS-channel structure shows a sharp and monocrystalline interface. The AlN interfacial layer not only results in lower interface trap density but also enables lower border traps in the vicinity of the gate-dielectric/GaN interface. Second, by adopting the high-quality Al2O3/AlN/GaN MOS-channel structure, a high-performance normally-off Al2O3/AlN/GaN MOS-channel-HEMT is demonstrated. This device exhibits reduced threshold voltage (Vth) hysteresis, excellent uniformity in Vth distribution, increased maximum drain current, enhanced maximum field-effect mobility, suppressed dynamic on-resistance degradation, and superior Vth thermal stability characteristics. The third section of this thesis focuses on the optimization of fabrication process and device structure. Using a combination of dry etching and digital etching techniques, the AlGaN barrier layer in the gate region is recessed down to 2-nm to create a normally-off recessed-thin-barrier GaN MIS-HEMT. The dry etching is able to enhance etching efficiency, whereas digital etching is capable of mitigating dry-etching-induced damages and precisely controlling the recess depth. The remaining thin-barrier layer not only permits a normally-off channel but also simultaneously reserves the original hetero-interface, resulting in high channel electron mobility and reduced on-resistance.

When
Time
3pm
Where
Room 3584 (Lifts 27-28), 3/F Academic Building, HKUST
Event Format
Speakers / Performers:
Mr Shenghou LIU
Language
English
Organizer
Department of Electronic & Computer Engineering
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