Thesis Examination Committee
Prof Gang WANG, CIVL/HKUST (Chairperson)
Prof Kevin CHEN, ECE/HKUST (Thesis Supervisor)
Prof Xu YANG, School of Electrical Engineering, Xi'an Jiaotong University (Thesis Co-supervisor)
Prof Shu-Hung Henry CHUNG, Department of Electronic Engineering, City University of Hong Kong (External Examiner)
Prof Wing Hung KI, ECE/HKUST
Prof George YUAN, ECE/HKUST
Prof Lilong CAI, MAE/HKUST
With superior performance and Si-compatible fabrication process, enhancement-mode p-GaN gate gallium nitride high-electron-mobility-transistors (E-mode GaN HEMTs) implemented on silicon substrate is emerging as a highly attractive enabling technology for power converters with high efficiency and high power density. To benefit from the high-frequency operation of these power devices, the unique device characteristics such as narrow gate swing and relatively low yet dynamic threshold voltage (Vth) need to be fully considered in circuit design optimization. In order to accurately predict transient waveforms for critical circuit reliability enhancement, a compact non-linear device model capable of capturing the devices’ dynamic behavior is highly desirable.
In this thesis, a physical-mechanism-based behavior device model is proposed for E-mode p-GaN gate GaN transistors, by considering Vth’s instability and static/dynamic behavior of p-GaN junction capacitances. Such a robust non-linear device model provides a powerful tool for systematic investigation on (1) the transient response of high-speed power switching circuits and (2) the challenge of safe gate drive brought by gate ringing phenomenon. To accurately evaluate device speed and gate charge, an approach of capturing internal p-GaN junction capacitance through external terminal measurement is developed. The benefit of the dynamic positive Vth-shift on mitigation of false turn-on phenomenon is revealed and experimentally validated for the first time.
Circuit-device interaction is of particular importance to assure safe and extensive deployment of high-speed GaN transistors. A systematic study of GaN transistor’s sensitivity to various circuit elements in power converters is conducted. The impacts of an integrated gate drive on switching speed and dead time are investigated with a behavior modeling approach. Aiming at suppressing the critical crosstalk phenomenon in extensively-used bridge-leg circuits, design guidelines for circuit optimization are developed and validated by considering the complicated resonance mechanisms between power-stage and gate-drive schemes.