Thesis Examination Committee
Prof Qingping SUN, MAE/HKUST (Chairperson)
Prof Kevin CHEN, ECE/HKUST (Thesis Supervisor)
Prof Hoi Wai CHOI, Department of Electrical and Electronic Engineering, The University of Hong Kong (External Examiner)
Prof Wing Hung KI, ECE/HKUST
Prof George YUAN, ECE/HKUST
Prof Lilong CAI, MAE/HKUST
Heterojunction-based GaN-on-Si power transistors have been under intensive development for next-generation power conversion systems with high efficiency and high power density over the last decade, owing to many benefits such as better loss-breakdown trade-off, higher switching frequency and higher operating temperatures than the mainstream Si counterparts. The CMOS-compatible fabrication process also makes GaN-on-Si power device technology cost competitive for market adoption. Nevertheless, these devices exhibit many distinctive characteristics that require clear understanding and device/circuit-level solutions for reliability and stability assurance. In this work, new device characterization techniques and power integration schemes are developed to fully exploit the benefits of GaN-on-Si power devices.
Firstly, the impact of substrate termination on the dynamic performance of lateral GaN-on-Si power devices is investigated. The different dynamic RON behaviors with grounded and floating substrate termination can be explained by the trade-off between charge storage in the Si substrate and trapping effect in the buffer layer. Compared to the grounded substrate termination, the floating substrate termination is found to be yield higher breakdown voltages and enable a better dynamic RON during high-voltage switching operations, and thus should be considered in package design of GaN-on-Si lateral power devices.
Secondly, aiming at an ultimate all-GaN solution, GaN power integration is developed based on a commercially available enhancement-mode (E-mode) GaN power device technology platform. On this platform, peripheral active devices and passive elements with lower voltage ratings are realized without any additional processing steps. GaN-based logic circuits with 0.1-ns propagation delay are monolithically integrated with 650-V/13 A power devices, paving the way toward GaN power switches with fully integrated control/sensing/protection/driving functional blocks.
Thirdly, to suppress the parasitic inductance in the gate drive loop and provide robust gate protection in high-frequency switching applications of GaN power switches, an all-GaN gate driver is designed and monolithically integrated with a GaN power switch. False turn-on and gate ringing are adequately suppressed as the power switch operates at slew rate well over 100 V/ns, proving the strong merit of the fully integrated gate driver in enabling greatly enhanced robustness and reliability for GaN power switches.