Advanced Processing Techniques for GaN Heterojunction Transistors
Room 3584 (Lifts 27-28), 3/F Academic Building, HKUST

Examination Committee

Prof Shuhuai YAO, MAE/HKUST (Chairperson)
Prof Kevin J CHEN, ECE/HKUST (Thesis Supervisor)
Prof Anthony H W CHOI, Department of Electrical and Electronic Engineering, The University of Hong Kong (External Examiner)
Prof Johnny K O SIN, ECE/HKUST
Prof Zhiyong FAN, ECE/HKUST



Wide bandgap GaN and related group III-nitride semiconductors possess many fundamental material properties that could lead to power switching devices outperforming the ones made of mainstream Si technology, enabling next-generation power conversion systems with higher efficiency and compact size. The most desirable device structure, i.e., insulated gate normally-off FET, however, is still challenged by reliability and stability issues originated from traps at the interface between the gate dielectric and III-nitride semiconductors, and traps in the buffer layer. This thesis focuses on developing advanced processing techniques to create high-quality interface and improve the gate dielectric quality for GaN metal-insulator-semiconductor high-electron-mobility transistors (MISHEMTs). To suppress the buffer trapping effect, an enhanced back barrier technique was realized with fluorine ion implantation.

To achieve low trap density at the interface between gate oxide and III-nitride semiconductors, AlN could play a special role as it was naturally compatible with III-nitride semiconductors and could be used to prevent oxygen from deteriorating the III-nitride surface. However, other than MOCVD and MBE growth techniques that require high thermal budget, low-temperature growth of AlN has been difficult. In this work, single-crystal-like AlN thin film has been successfully grown at 300 oC using plasma-enhanced atomic layer deposition (PE-ALD) technique. In-depth characterizations were conducted on AlN/GaN MIS structures to identify the unique properties of PE-ALD-grown AlN. The resulting high-quality AlN film shows great potential in enhancing device performance when integrated into GaN devices.

Although the interface trap density can be significantly reduced by using an AlN-based nitridation interfacial-layer, thermally-assisted electron emission from deep interface trap states could lead to thermal instability in threshold voltage (VTH). To address this issue, normally-off MISHEMTs featuring a partially recessed AlGaN barrier were proposed and realized by a fluorine-plasma hybrid implantation/etch technique. These devices exhibit low on-resistance (as high channel mobility is maintained) and positive VTH for normally-off operation. Furthermore, the MISHEMT exhibits enhanced VTHthermal stability, as the separation between the critical dielectric/III-nitride interface and the 2DEG channel is reduced. 

Lastly, GaN MISHEMTs with fluorine-implanted enhanced back barrier were implemented. The negatively charged F− ions in back barrier raise the potential of GaN buffer under the gate, leading to lower source-drain leakage current of devices at OFF-state. Furthermore, improved dynamic performance during high-voltage switching operations was also obtained. In particular, the presence of low-density fluorine ions in the channel region introduces impurity scattering that can effectively suppress the generation of hot electrons, leading to smaller dynamic on-resistance degradation.

Room 3584 (Lifts 27-28), 3/F Academic Building, HKUST
Event Format
Speakers / Performers:
Mr Cheng LIU
Department of Electronic & Computer Engineering
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